EP1K100FI256-2

Product Summary

The EP1K100FI256-2 is a Programmable Logic Device providing a die-efficient, low-cost architecture by combining look-up table (LUT) architecture with EABs. LUT-based logic provides optimized performance and efficiency for data-path, register intensive, mathematical, or digital signal processing (DSP) designs, while EABs implement RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions. These elements make the EP1K100FI256-2 suitable for complex logic functions and memory functions such as digital signal processing, wide data-path manipulation, data transformation and microcontrollers, as required in high-performance communications applications. Based on reconfigurable CMOS SRAM elements, the EP1K100FI256-2 architecture incorporates all features necessary to implement common gate array megafunctions, along with a high pin count to enable an effective interface with system components. The advanced process and the low voltage requirement of the 2.5-V core allow the EP1K100FI256-2 to meet the requirements of low-cost, high-volume applications ranging from DSL modems to low-cost switches.

Parametrics

EP1K100FI256-2 absolute maximum ratings: (1)VCCINT, Supply voltage: –0.5 to 3.6 V; (2)VCCIO: –0.5 to 4.6 V; (3)VI, DC input voltage: –2.0 to 5.75 V; (4)IOUT, DC output current, per pin: –25 to 25 mA; (5)TSTG, Storage temperature No bias: –65 to 150℃; (6)TAMB, Ambient temperature Under bias: –65 to 135℃; (7)TJ, Junction temperature: 135℃.

Features

EP1K100FI256-2 features: (1)Operate with a 2.5-V internal supply voltage; (2)In-circuit reconfigurability (ICR) via external configuration devices, intelligent controller, or JTAG port; (3)ClockLockTM and ClockBoostTM options for reduced clock delay, clock skew, and clock multiplication; (4)Built-in, low-skew clock distribution trees; (5)100% functional testing of all devices; test vectors or scan chains are not required; (6)Pull-up on I/O pins before and during configuration; (7)Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions ; (8)Dual-port capability with up to 16-bit width per embedded array block (EAB); (9)Logic array for general logic functions.

Diagrams