TMS320C6412AZDK

Product Summary

The TMS320C6412AZDK is a Fixed-Point Digital Signal Processor. The TMS320C6412AZDK is the highest-performance fixed-point DSP generation in the TMS320C6000TM DSP platform. The TMS320C6412AZDK is based on the second-generation high-performance, advanced VelociTITM very-long-instruction-word (VLIW) architecture (VelociTI.2TM) developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. The C64xTM is a code-compatible member of the C6000TM DSP platform.

Parametrics

TMS320C6412AZDK absolute maximum ratings: (1)Supply voltage ranges CVDD : -0.3 V to 1.8 V; (2)DVDD : -0.3 V to 4 V; (3)Input voltage ranges (except PCI), VI : -0.3 V to 4 V; (4)(PCI), VIP : -0.5 V to DVDD + 0.5 V; (5)Output voltage ranges (except PCI), VO : -0.3 V to 4 V; (6)(PCI), VOP : -0.5 V to DVDD + 0.5 V; (7)Operating case temperature ranges, TC (default) : 0℃ to 90℃; (8)(A version) [A-500 only] : 40℃ to 105℃; (9)Storage temperature range, Tstg : -65℃ to 150℃; (10)Package Temperature Cycling Temperature Range : -40℃ to 125℃; (11)Number of Cycles : 500.

Features

TMS320C6412AZDK features: (1)Endianess: Little Endian, Big Endian; (2)64-Bit External Memory Interface (EMIF)Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM SBSRAM, ZBT SRAM, and FIFO); (3)1024M-Byte Total Addressable External Memory Space; (4)Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels); (5)Management Data Input/Output (MDIO); (6)Host-Port Interface (HPI) [32-/16-Bit]; (7)32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2; (8)Inter-Integrated Circuit (I2C) Bus; (9)Two Multichannel Buffered Serial Ports; (10)Three 32-Bit General-Purpose Timers; (11)Sixteen General-Purpose I/O (GPIO) Pins; (12)Flexible PLL Clock Generator; (13)IEEE-1149.1 (JTAG）Boundary-Scan-Compatible; (14)548-Pin Ball Grid Array (BGA) Package (GDK Suffix), 0.8-mm Ball Pitch; (15)548-Pin Ball Grid Array (BGA) Package (GNZ Suffix), 1.0-mm Ball Pitch; (16)0.13-μm/6-Level Cu Metal Process (CMOS); (17)3.3-V I/Os, 1.2-V Internal (-500); (18)3.3-V I/Os, 1.4-V Internal (A-500, -600).

Diagrams